Semiconductor device and method of fabricating the same

ABSTRACT

A semiconductor device includes a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, a source/drain diffusion layer formed in the semiconductor substrate at both sides of the gate electrode, and a channel region formed in the semiconductor substrate between a source and a drain of the source/drain diffusion layer and arranged below the gate insulating film, wherein an upper surface of the source/drain diffusion layer is positioned below a bottom surface of the gate electrode, and an upper surface of the channel region is positioned below the upper surface of the source/drain diffusion layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromprior Japanese Patent Application No. 2005-065812, filed Mar. 9, 2005,the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device and a method offabricating the same.

2. Description of the Related Art

As downsizing of transistor elements advances, a so-called short-channeleffect becomes a problem. As a method of avoiding this short-channeleffect, an elevated source/drain structure is conventionally known.

FIG. 26 is a schematic view showing a semiconductor device having anelevated source/drain structure according to prior art. As shown in FIG.26, a gate electrode 3 is formed on a silicon substrate 1 via a gateoxide film 2, and a metal silicide layer 4 is formed on the gateelectrode 3. A gate sidewall oxide film 14 and sidewall insulating film16 are formed on the side surfaces of the gate electrode 3. The gateoxide film 2 is removed from the surface of the silicon substrate 1outside the sidewall insulating film 16, and epitaxially grown siliconlayers 20 are formed above the substrate surface position (indicated bythe dotted lines in FIG. 26). An element serving as an impurity ision-implanted into the silicon layers 20, and activation annealing isperformed, thereby forming elevated source/drain diffusion layers 17.

In the above prior art, ion implantation is performed through thesilicon layers 20 formed above the substrate surface position, so thesource/drain diffusion layers 17 can be made shallow. Accordingly, thissemiconductor device having the elevated source/drain structure canavoid the short-channel effect.

Unfortunately, this prior art has the problem that an overlapcapacitance C between the gate electrode 3 and the source/draindiffusion layer 17 increases, and this decreases the operating speed ofa transistor Tr. In addition, the number of fabrication steps increases,and this increases the device cost. Furthermore, a high-temperature stepof epitaxial growth deteriorates the characteristics of the transistorTr.

Note that prior art reference information related to the invention ofthis application is, e.g., U.S. Pat. No. 6,335,251.

BRIEF SUMMARY OF THE INVENTION

A semiconductor device according to a first aspect of the presentinvention comprises a semiconductor substrate, a gate insulating filmformed on the semiconductor substrate, a gate electrode formed on thegate insulating film, a source/drain diffusion layer formed in thesemiconductor substrate at both sides of the gate electrode, and achannel region formed in the semiconductor substrate between a sourceand a drain of the source/drain diffusion layer and arranged below thegate insulating film, wherein an upper surface of the source/draindiffusion layer is positioned below a bottom surface of the gateelectrode, and an upper surface of the channel region is positionedbelow the upper surface of the source/drain diffusion layer.

A semiconductor device manufacturing method according to a second aspectof the present invention comprises forming a gate insulating film on asemiconductor substrate, selectively forming a gate electrode on thegate insulating film, forming a nitrogen-containing insulating film bynitriding an exposed portion of the gate insulating film, performingthermal oxidation that an oxide amount at an upper surface of thesemiconductor substrate and at a bottom surface of the gate electrodereduces from an end portion to a central portion of a channel regionbeneath the gate electrode, forming a sidewall layer on a side surfaceof the gate electrode, and thickening the gate insulating film in alower end portion of the gate electrode, and forming a source/draindiffusion layer in the semiconductor substrate.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

FIG. 1 is a sectional view showing a semiconductor device according tothe first embodiment of the present invention;

FIG. 2 is a partially enlarged schematic view of the semiconductordevice shown in FIG. 1;

FIGS. 3 to 8 are sectional views showing the fabrication steps of thesemiconductor device according to the first embodiment of the presentinvention;

FIG. 9 is a view showing the nitrogen concentration distribution insilicon oxynitride layers according to the first embodiment of thepresent invention;

FIGS. 10A and 10B are sectional views showing the fabrication steps ofanother semiconductor device according to the first embodiment of thepresent invention, in which after silicon oxynitride layers are formed,a gate oxide film in gaps is removed;

FIGS. 11A and 11B are sectional views showing the fabrication steps ofstill another semiconductor device according to the first embodiment ofthe present invention, in which after a gate electrode is formed, a gateoxide film exposed from the gate electrode is removed;

FIG. 12 is a sectional view showing the fabrication steps of stillanother semiconductor device according to the first embodiment of thepresent invention, in which in a mask material removing step, exposedportions of silicon oxynitride layers are not removed;

FIG. 13 is a sectional view showing a semiconductor device according tothe second embodiment of the present invention;

FIG. 14 is a partially enlarged schematic view of the semiconductordevice shown in FIG. 13;

FIGS. 15A to 22 are sectional views showing the fabrication steps of anonvolatile semiconductor memory according to the second embodiment ofthe present invention, in which FIGS. 15A, 16A, 17A, 18A, and 19 to 22are sectional views in a bit line direction (channel length direction),and FIGS. 15B, 16B, 17B, and 18B are sectional views in a word linedirection (channel width direction);

FIG. 23 is a view showing the nitrogen concentration distribution in asilicon oxynitride layer according to the second embodiment of thepresent invention;

FIGS. 24A and 24B are sectional views showing the fabrication steps ofanother nonvolatile semiconductor memory according to the secondembodiment of the present invention, in which after silicon oxynitridelayers are formed, a tunnel oxide film in gaps is removed;

FIGS. 25A and 25B are sectional views showing the fabrication steps ofstill another nonvolatile semiconductor memory according to the secondembodiment of the present invention, in which after floating gateelectrodes are formed, a tunnel oxide film exposed from the floatinggate electrodes is removed; and

FIG. 26 is a schematic view showing a semiconductor device having anelevated source/drain structure according to prior art.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the present invention will be described below withreference to the accompanying drawing. In the following description, thesame reference numerals denote the same parts throughout the drawing.

First Embodiment

FIG. 1 is a sectional view of a semiconductor device according to thefirst embodiment of the present invention. FIG. 2 is a partiallyenlarged schematic view of the semiconductor device shown in FIG. 1.This semiconductor device according to the first embodiment will beexplained below.

As shown in FIG. 1, a gate electrode G is formed on a silicon substrate(semiconductor substrate) 1 via a gate oxide film 2, and a channelregion C is formed in the silicon substrate 1 below the gate electrodeG. A gate sidewall oxide film 14 is formed on the side surfaces of thegate electrode G. A sidewall insulating film 16 is formed on the sidesurfaces of the gate sidewall oxide film 14. Source/drain diffusionlayers 17 are formed in the silicon substrate 1 so as to sandwich thegate electrode G between them. An element isolation insulating film 6having an STI (Shallow Trench Isolation) structure is formed adjacent tothe source/drain diffusion layers 17. Silicon oxynitride layers(nitrogen-containing insulating films) 12 are formed on portions of thesource/drain diffusion layers 17. The silicon oxynitride layers 12 arepositioned below the sidewall insulating film 16. A metal silicide layer18 a is formed on the upper surface of the gate electrode G, and metalsilicide layers 18 b are formed on the source/drain diffusion layers 17.In addition, interface nitride layers 15 are formed in the interfacebetween the gate electrode G and gate oxide film 2, in the interfacebetween the gate electrode G and gate sidewall oxide film 14, and in theinterface between the gate oxide film 2 and silicon substrate 1.

The gate oxide film 2 has a central portion 2 a positioned below thegate electrode G, and end portions 2 b positioned below the gatesidewall oxide film 14. The film thickness of the end portions 2 b ofthe gate oxide film 2 is larger than that of the central portion 2 a ofthe gate oxide film 2, so the film thickness of the gate oxide film 2gradually increases from the central portion 2 a toward the end portions2 b. Also, the boundary between the gate oxide film 2 and gate sidewalloxide film 14 is unclear; the gate oxide film 2 and gate sidewall oxidefilm 14 are substantially integrated when formed by thermal oxidation.

The film thickness of the gate sidewall oxide film 14 decreases from thebottom surface to the upper surface of the gate electrode G. In otherwords, the gate length (the width in the lateral direction of the paper)of the gate electrode G increases from the bottom surface to the uppersurface.

As shown in FIG. 2, a position B of the upper surface of thesource/drain diffusion layer 17 is lower than a position A of the bottomsurface (the upper surface of the central portion 2 a of the gate oxidefilm 2) of the gate electrode G. Also, positions Ca and Cb of the uppersurface (the bottom surfaces of the central portion 2 a and end portion2 b of the gate oxide film 2) of the channel region C are lower than theposition B of the upper surface of the source/drain diffusion layer 17.Furthermore, the position Cb of the upper surface (the bottom surface ofthe end portion 2 b of the gate oxide film 2) of the channel region C inthe end portion 2 b of the gate oxide film 2 is lower than the positionCa of the upper surface (the bottom surface of the central portion 2 aof the gate oxide film 2) of the channel region C in the central portion2 a of the gate oxide film 2.

In other words, recession amounts Rca and Rcb from a position S of theupper surface of the silicon substrate 1 to the positions Ca and Cb,respectively, of the upper surface of the channel region C are largerthan a recession amount Rb from the position S of the upper surface ofthe silicon substrate 1 to the position B of the upper surface of thesource/drain diffusion layer 17. In addition, the recession amount Rcbfrom the position S of the upper surface of the silicon substrate 1 tothe position Cb of the upper surface of the channel region C in the endportion 2 b of the gate oxide film 2 is larger than the recession amountRca from the position S of the upper surface of the silicon substrate 1to the position Ca of the upper surface of the channel region C in thecentral portion 2 a of the gate oxide film 2.

Also, a position D of the upper surface of the silicon oxynitride layer12 is equal to or lower than the position A of the bottom surface of thegate electrode G.

Note that the source/drain diffusion layer 17 can take various shapes.For example, a so-called extension diffusion layer (or shallow junctionregion) or the like may also be formed. Also, to suppress theshort-channel effect, the dopant impurity concentration at the substratesurface is desirably maximized.

FIGS. 3 to 8 are sectional views showing the fabrication steps of thesemiconductor device according to the first embodiment of the presentinvention. The fabrication method of the semiconductor device accordingto the first embodiment will be explained below.

First, as shown in FIG. 3, a gate oxide film 2 having a thickness of,e.g., 5 nm is formed by thermal oxidation on the surface of a siliconsubstrate 1 in which a desired impurity is doped. Then, an elementisolation insulating film 6 serving as element isolation regions isformed in the silicon substrate 1. An example of the material of theelement isolation insulating film 6 is a silicon oxide film. After that,a polysilicon layer 3 serving as a gate electrode G and a mask material4 are sequentially deposited by CVD (Chemical Vapor Deposition). Anexample of the mask material 4 is a silicon nitride film.

As shown in FIG. 4, a gate electrode G is formed by processing the maskmaterial 4 and polysilicon layer 3 by RIE (Reactive Ion Etching). Inthis state, a gate length (channel length) L1 is, e.g., about 50 nm.

As shown in FIG. 5, active nitrogen ions (indicated by arrows in FIG. 5)are incident to nitride exposed portions of the gate oxide film 2. Thisnitriding is so performed that in a region between the gate electrode Gand element isolation insulating film 6, the nitrogen concentration ismaximized in the boundary to the element isolation insulating film 6 andminimized in the boundary to the gate electrode G. Consequently, on thesilicon substrate 1 between the gate electrode G and element isolationinsulating film 6, silicon oxynitride layers 12 in which the nitrogenconcentration is higher than the oxygen concentration are formed. Gaps13 are formed between one end of each silicon oxynitride layer 12 andthe end portion of the gate electrode G (one end of each siliconoxynitride layer 12 is not in contact with the end portion of the gateelectrode G), and the other end of the silicon oxynitride layer 12 is incontact with the element isolation insulating film 6. Note thatnitriding by active nitrogen ions may also be nitriding by chargedradical nitrogen performed by using a radical nitriding process, ornitrogen ions may also be drawn by applying a bias to the substrate.

In this embodiment, the gaps 13 are formed because they are hidden bythe gate electrode G. However, the gaps 13 need not be formed if thenitrogen concentration is low in the boundaries between the gateelectrode G and silicon oxynitride layers 12.

As shown in FIG. 6, a gate sidewall oxide film 14 having a thickness of,e.g., 10 nm is formed on the sidewalls of the gate electrode G. In thiscase, the surface portion of the silicon substrate 1 and the bottomportion of the gate electrode G are so oxidized that the oxide amount inthe silicon substrate 1 reduces from the end portions to the centralportion of the channel region. Since the silicon oxynitride layers 12 onthe surface of the silicon substrate 1 function as anti-oxidationlayers, the oxidation reaction does not progress in these portions, sobird's beak oxidation of the channel region advances. Consequently, thethickness of the gate oxide film 2 at the lower end portions of the gateelectrode G increases, so the film thickness of end portions 2 b of thegate oxide film 2 becomes lager than that of a central portion 2 a ofthe gate oxide film 2. For example, the film thickness of the endportions 2 b of the gate oxide film 2 is as large as about 10 nm, andthat of the central portion 2 a of the gate oxide film 2 is about 6 nm.

As shown in FIG. 7, oxynitriding is performed in an NO gas or N₂O gasambient at 900° C. to form interface nitride layers 15 in the interfacebetween the gate electrode G and gate oxide film 2, in the interfacebetween the gate electrode G and gate sidewall oxide film 14, and in theinterface between the gate oxide film 2 and silicon substrate 1. Asidewall insulating film 16 is formed on the side surfaces of the gateelectrode G by using a known technique. Note that the interface nitridelayers 15 may also be formed after the sidewall insulating film 16 isformed. After that, source/drain diffusion layers 17 are formed in thesilicon substrate 1 below the silicon oxynitride layers 12.

As shown in FIG. 8, the mask material 4 is selectively removed. As aconsequence, the silicon oxynitride layers 12 exposed from the sidewallinsulating film 16 are also removed to expose the upper surfaces of thesource/drain diffusion layers 17.

Then, as shown in FIG. 1, the upper surfaces of the gate electrode G andsource/drain diffusion layers 17 are silicided to form metal silicidelayers 18 a and 18 b. Examples of the metal silicide layers 18 a and 18b are cobalt silicide, tungsten silicide, and titanium silicide. In thismanner, a semiconductor device having a transistor Tr is completed.

FIG. 9 shows the nitrogen concentration distribution in the siliconoxynitride layers according to the first embodiment of the presentinvention. This nitrogen concentration distribution in the siliconoxynitride layers according to the first embodiment will be explainedbelow.

As shown in FIG. 9, the nitrogen concentration in each siliconoxynitride layer 12 gradually increases from a first end portionadjacent to the gate electrode G to a second end portion opposite to thefirst end portion. Accordingly, in the silicon oxynitride layer 12, thenitrogen concentration is lowest in the first end portion and highest inthe second end portion.

In the first embodiment described above, the position B of the uppersurface of the source/drain diffusion layers 17 is lower than theposition A of the bottom surface of the gate electrode G, and thepositions Ca and Cb of the upper surface of the channel region C arelower than the position B of the upper surface of the source/draindiffusion layers 17 (FIG. 2). That is, the position of the upper surfaceof the channel region C can be made lower than that in the conventionaldevices. In particular, depletion layers of the source/drain diffusionlayers 17 can be separated between the source and drain by the endportions 2 b of the gate oxide film 2. It is also possible toeffectively substantially increase the channel length (source-to-draindistance). Therefore, punch through can be suppressed even when thechannel length increases. This makes it possible to suppress theshort-channel effect and downsize the transistor Tr.

In addition, the film thickness of the central portion 2 a of the gateoxide film 2 is smaller than that of the end portions 2 b. Thisincreases the gate potential's control over the channel potential, sothe short-channel effect can be suppressed more effectively.

Furthermore, the film thickness of the end portions 2 b of the gateoxide film 2 positioned in the end portions of the gate electrode G islarge. This makes it possible to reduce the parasitic capacitancebetween the gate electrode G and source/drain diffusion layers 17, sothe decrease in operating speed of the transistor can be furthersuppressed. Also, since the electric fields between the end portions ofthe gate electrode G and the source/drain diffusion layers 17 can bereduced, changes in transistor characteristics with operation time canbe suppressed. Accordingly, the reliability of the transistor Tr can beimproved.

Since the film thickness of the end portions 2 b of the gate oxide film2 is large, the distance between the gate electrode G and thesource/drain diffusion layer 17 can be increased. In this case, comparedto the conventional elevated source/drain structure, the overlapcapacitance C between the gate electrode G and source/drain diffusionlayer 17 can be reduced. This eliminates the problem of the decrease inoperating speed of the transistor Tr.

The gate length (channel length) L1 is approximately 50 nm or less. Withthis prescribed value, the central portion 2 a (channel central portion)of the gate oxide film 2 can be well oxidized in the channel portionthermal oxidation step shown in FIG. 6.

Also, the interface nitride layers 15 are formed in the interfacebetween the gate electrode G and gate oxide film 2, in the interfacebetween the gate electrode G and gate sidewall oxide film 14, and in theinterface between the gate oxide film 2 and silicon substrate 1.Therefore, it is possible to prevent mixing of an impurity from the gateelectrode G or silicon substrate 1 to the gate oxide film 2.

Note that in the first embodiment, after the silicon oxynitride layers12 are formed (FIG. 5), it is also possible to remove the gate oxidefilm 2 in the gaps 13 (or low-nitrogen-concentration regions in theboundaries to the gate electrode G) by, e.g., a dilute hydrofluoric acidsolution (FIG. 10A), and then form a gate sidewall oxide film 14 bythermal oxidation. In this case, as shown in FIG. 10B, oxidation readilyprogresses near the gaps 13, so the film thickness of the end portions 2b of the gate oxide film 2 can be further increased. Accordingly, theposition Cb of the upper surface of the end portion of the channelregion C lowers, so the recession amount Rcb can be further increased.This makes it possible to suppress the short-channel effect moreeffectively.

Likewise, after the gate electrode G is formed (FIG. 4), it is alsopossible to remove the gate oxide film 2 exposed from the gate electrodeG by, e.g., a dilute hydrofluoric acid solution (FIG. 11A), and thenform silicon oxynitride layers 12. In this structure as shown in FIG.11B, compared to the structure shown in FIG. 1, the position B of theupper surfaces of the source/drain layers 17 decreases, and therecession amount Rb increases, but the position Cb of the upper surfacesof the end portions of the cannel region C also decreases, and therecession amount Rcb also increases. Therefore, the short-channel effectcan be suppressed as in the structure shown in FIG. 1. In addition, itis possible to form silicon oxynitride layers 12 having an oxidationproof property higher than that of the structure shown in FIG. 1.

Furthermore, the exposed portions of the silicon oxynitride layers 12may also be kept unremoved in the step of removing the mask material 4shown in FIG. 8, by forming the mask material 4 by using a material(e.g., a silicon oxide film) having high selectivity to the siliconoxynitride layers 12. In this case, as shown in FIG. 12, the siliconoxynitride layers 12 remain on the upper surfaces of the source/draindiffusion layers 17, so the metal silicide layers 18 b shown in FIG. 1are not formed. In this structure, between the gate electrode G andelement isolation insulating film 6, the nitrogen concentration ismaximized in the boundary between the silicon oxynitride layer 12 andelement isolation insulating film 6, and minimized in the boundarybetween the silicon oxynitride layer 12 and gate electrode G.

Second Embodiment

The second embodiment shows an example of a nonvolatile semiconductormemory including a memory cell transistor having a floating gateelectrode and control gate electrode.

FIG. 13 is a sectional view of the nonvolatile semiconductor memoryaccording to the second embodiment of the present invention. FIG. 14 isa partially enlarged schematic view of the nonvolatile semiconductormemory shown in FIG. 13. This nonvolatile semiconductor memory accordingto the second embodiment will be described below.

As shown in FIG. 13, the second embodiment differs from the firstembodiment in that a memory cell transistor Tr of a nonvolatilesemiconductor memory is taken as an example. Therefore, the structure ofthe second embodiment is as follows.

A floating gate electrode FG is formed on a silicon substrate 101 via atunnel oxide film 102, and a control gate electrode CG is formed on thefloating gate electrode FG via an inter-electrode insulating film 108. Asilicon nitride film 110 is formed on the control gate electrode CG. Asidewall cover film 111 is formed on the side surfaces of the siliconnitride film 110, control gate electrode CG, and inter-electrodeinsulating film 108. A gate sidewall oxide film 114 is formed on theside surfaces of the floating gate electrode FG. A channel region C isformed in the silicon substrate 101 below the floating gate electrodeFG. Silicon oxynitride layers 112 are formed on inter-cell regions ofthe silicon substrate 101. Source/drain diffusion layers 117 are formedin the silicon substrate 101 below the silicon oxynitride layers 112. Inaddition, interface nitride layers 115 are formed in the interfacebetween the floating gate electrode FG and tunnel oxide film 102, in theinterface between the floating gate electrode FG and gate sidewall oxidefilm 114, and in the interface between the tunnel oxide film 102 andsilicon substrate 101.

The tunnel oxide film 102 has a central portion 102 a positioned belowthe floating gate electrode FG, and end portions 102 b positioned belowthe gate sidewall oxide film 114. The film thickness of the end portions102 b of the tunnel oxide film 102 is larger than that of the centralportion 102 a of the tunnel oxide film 102, so the film thickness of thetunnel oxide film 102 gradually increases from the central portion 102 atoward the end portions 102 b. Also, the boundary between the tunneloxide film 102 and gate sidewall oxide film 114 is unclear; the tunneloxide film 102 and gate sidewall oxide film 114 are substantiallyintegrated when formed by thermal oxidation.

The film thickness of the gate sidewall oxide film 114 decreases fromthe bottom surface to the upper surface of the floating gate electrodeFG. In other words, the gate length (the width in the lateral directionof the paper) of the floating gate electrode FG increases from thebottom surface to the upper surface.

As shown in FIG. 14, a position B of the upper surface of thesource/drain diffusion layer 117 is lower than a position A of thebottom surface (the upper surface of the central portion 102 a of thetunnel oxide film 102) of the floating gate electrode FG. Also,positions Ca and Cb of the upper surface (the bottom surfaces of thecentral portion 102 a and end portion 102 b of the tunnel oxide film102) of the channel region C are lower than the position B of the uppersurface of the source/drain diffusion layer 117. Furthermore, theposition Cb of the upper surface (the bottom surface of the end portion102 b of the tunnel oxide film 102) of the channel region C in the endportion 102 b of the tunnel oxide film 102 is lower than the position Caof the upper surface (the bottom surface of the central portion 102 a ofthe tunnel oxide film 102) of the channel region C in the centralportion 102 a of the tunnel oxide film 102.

In other words, recession amounts Rca and Rcb from a position S of theupper surface of the silicon substrate 101 to the positions Ca and Cb,respectively, of the upper surface of the channel region C are largerthan a recession amount Rb from the position S of the upper surface ofthe silicon substrate 101 to the position B of the upper surface of thesource/drain diffusion layer 117. In addition, the recession amount Rcbfrom the position S of the upper surface of the silicon substrate 101 tothe position Cb of the upper surface of the channel region C in the endportion 102 b of the tunnel oxide film 102 is larger than the recessionamount Rca from the position S of the upper surface of the siliconsubstrate 101 to the position Ca of the upper surface of the channelregion C in the central portion 102 a of the tunnel oxide film 102.

Also, a position D of the upper surface of the silicon oxynitride layer112 is equal to or lower than the position A of the bottom surface ofthe floating gate electrode FG.

FIGS. 15A to 22 are sectional views showing the fabrication steps of thenonvolatile semiconductor memory according to the second embodiment ofthe present invention. FIGS. 15A, 16A, 17A, 18A, and 19 to 22 aresectional views in a bit line direction (channel length direction).FIGS. 15B, 16B, 17B, and 18B are sectional views in a word linedirection (channel width direction). The fabrication method of thenonvolatile semiconductor memory according to the second embodiment willbe explained below.

First, as shown in FIGS. 15A and 15B, a tunnel oxide film 102 having athickness of, e.g., 5 nm is formed by thermal oxidation on the surfaceof a silicon substrate 101 in which a desired impurity is doped. Then, aphosphorus-doped polysilicon layer 103 serving as floating gateelectrodes FG and having a thickness of, e.g., 100 nm and a maskmaterial 104 for element isolation processing are sequentially depositedby CVD (Chemical Vapor Deposition). After that, RIE using a resist mask(not shown) is performed to sequentially etch the mask material 104,polysilicon layer 103, and tunnel oxide film 102, and etch the exposedregions of the silicon substrate 101. As a consequence, elementisolation trenches 105 having a depth d of, e.g., 100 nm are formed. Achannel width W is, e.g., about 50 nm.

As shown in FIGS. 16A and 16B, an element isolation insulating film 106made of, e.g., a silicon oxide film is deposited on the siliconsubstrate 101 and mask material 104, and embedded in the elementisolation trenches 105. After that, CMP (Chemical Mechanical Polishing)is performed to planarize the upper surface of the element isolationinsulating film 106 until the mask material 104 is exposed.

As shown in FIGS. 17A and 17B, the mask material 104 is selectivelyetched away. Then, a dilute hydrofluoric acid solution is used to etchaway the upper portion of the element isolation insulating film 106until its upper surface is positioned below the upper surface of thepolysilicon layer 103. In this manner, sidewall surfaces 107 of thepolysilicon layer 103 are exposed. A height H of the sidewall surfaces107 is, e.g., 50 nm.

As shown in FIGS. 18A and 18B, an inter-electrode insulating film 108having a film thickness of, e.g., 15 nm is deposited on the polysiliconlayer 103 and element isolation insulating film 106 by CVD. Theinter-electrode insulating film 108 is an ONO (Oxide Nitride Oxide) filmhaving a three-layered structure including, e.g., a silicon oxidefilm/silicon nitride film/silicon oxide film each having a filmthickness of, e.g., 5 nm. After that, a conductive layer 109 serving ascontrol gate electrodes CG and having a thickness of, e.g., 100 nm isdeposited on the inter-electrode insulating film 108. The conductivelayer 109 has a two-layered structure including a polysiliconlayer/tungsten silicide layer. Furthermore, a silicon nitride film 110serving as a mask material in RIE is deposited on the conductive layer109 by CVD.

Then, as shown in FIG. 19, the silicon nitride film 110, conductivelayer 109, and inter-electrode insulating film 108 are sequentiallyetched by RIE using a resist mask (not shown). In this way, control gateelectrodes CG made of the conductive layer 109 are patterned. Afterthat, a sidewall cover film 111 having a thickness of, e.g., 5 nm isformed on the side surfaces of the silicon nitride film 110, controlgate electrodes CG, and inter-electrode insulating film 108 bylow-pressure CVD. Note that in this embodiment, a silicon nitride filmis formed as the sidewall cover film 111 by using low-pressure CVD.However, it is also possible to form a nitride layer by using plasmanitriding, or to perform oxynitriding by using an oxynitriding gas suchas NO or N₂O gas.

As shown in FIG. 20, the polysilicon layer 103 is processed by RIE,thereby patterning floating gate electrodes FG made of the polysiliconlayer 103. A channel length L2 is, e.g., about 50 nm.

As shown in FIG. 21, active nitrogen ions (indicated by arrows in FIG.21) are incident from openings between adjacent cells to nitrideportions of the tunnel oxide film 102. This nitriding is so performedthat the nitrogen concentration is maximized in the central portions ofthe inter-cell regions, and minimized in their end portions.Consequently, on the silicon substrate 101 in the central portions ofthe inter-cell regions, silicon oxynitride layers 112 in which thenitrogen concentration is higher than the oxygen concentration areformed. Gaps 113 are desirably formed between the silicon oxynitridelayers 112 and floating gate electrodes FG so that the siliconoxynitride layers 112 are not in contact with the floating gateelectrodes FG. Note that if the nitrogen concentration is low, thesilicon oxynitride layers 112 can be in contact with the floating gateelectrodes FG. Note also that nitriding by active nitrogen ions may alsobe nitriding by charged radical nitrogen performed by using a radicalnitriding process, or nitrogen ions may also be drawn by applying a biasto the substrate.

As shown in FIG. 22, a gate sidewall oxide film 114 having a thicknessof, e.g., 10 nm is formed on the side surfaces of each floating gateelectrode FG. In this case, the surface portion of the silicon substrate101 and the bottom portion of the floating gate electrode FG are sooxidized that the oxide amount in the silicon substrate 101 reduces fromthe end portions to the central portion of each channel region. Sincethe silicon oxynitride layers 112 on the substrate surface between thecells function as anti-oxidation layers, the oxidation reaction does notprogress in the inter-cell regions, so bird's beak oxidation of thechannel regions advances. Consequently, the film thickness of endportions 102 b of the tunnel oxide film 102 becomes larger than that ofa central portion 102 a of the tunnel oxide film 102. That is, the filmthickness of the end portions 102 b of the tunnel oxide film 102 is aslarge as about 10 nm, and that of the central portion 102 a of thetunnel oxide film 102 is about 6 nm. Note that no bird's beak oxidationoccurs on the side surfaces of the inter-electrode insulating film 108because they are covered with the sidewall cover film 111.

Then, as shown in FIG. 13, oxynitriding is performed in an NO gas or N₂Ogas ambient at 900° C. to form interface nitride layers 115 in theinterface between the floating gate electrode FG and tunnel oxide film102, in the interface between the floating gate electrode FG and gatesidewall oxide film 114, and in the interface between the gate oxidefilm 102 and silicon substrate 101. After that, source/drain diffusionlayers 117 are formed in the silicon substrate 101 below the siliconoxynitride layers 112 by using a known technique. In this manner,nonvolatile memory transistors Tr are completed.

FIG. 23 shows the nitrogen concentration distribution in the siliconoxynitride layer according to the second embodiment of the presentinvention. This nitrogen concentration distribution in the siliconoxynitride layer according to the second embodiment will be explainedbelow.

As shown in FIG. 23, the nitrogen concentration in the siliconoxynitride layer 112 gradually increases from its end portions to itscentral portion. Accordingly, in the silicon oxynitride layer 112, thenitrogen concentration is lowest in its end portions and highest in itscentral portion.

In the second embodiment described above, substantially the same effectsas in the first embodiment can be obtained as follows.

The position B of the upper surface of the source/drain diffusion layers117 is lower than the position A of the bottom surface of the floatinggate electrode FG, and the positions Ca and Cb of the upper surface ofthe channel region C are lower than the position B of the upper surfaceof the source/drain diffusion layers 117 (FIG. 14). That is, theposition of the upper surface of the channel region C can be made lowerthan that in the conventional devices. In particular, depletion layersof the source/drain diffusion layers 117 can be separated between thesource and drain by the end portions 102 b of the tunnel oxide film 102.It is also possible to effectively substantially increase the channellength (source-to-drain distance). Therefore, in the nonvolatile memorycell transistor Tr generally having a low channel impurityconcentration, punch through can be suppressed even when the channellength increases. This makes it possible to suppress the short-channeleffect, and greatly downsize the memory cell transistor Tr.

In addition, the film thickness of the central portion 102 a of thetunnel oxide film 102 is smaller than that of the end portions 102 b.This increases the gate potential's control over the channel potential,so the short-channel effect can be suppressed more effectively.

Furthermore, the film thickness of the end portions 102 b of the tunneloxide film 102 positioned in the end portions of the floating gateelectrode FG is large. This makes it possible to reduce the parasiticcapacitance between the floating gate electrode FG and source/draindiffusion layers 117, so the decrease in operating speed of the memorycell transistor Tr can be further suppressed. Also, since the electricfields between the end portions of the floating gate electrode FG andthe source/drain diffusion layers 117 can be reduced, the reliability ofthe memory cell transistor Tr whose reliability is regarded as importantcan be greatly improved.

Since the film thickness of the end portions 102 b of the tunnel oxidefilm 102 is large, the distance between the floating gate electrode FGand the source/drain diffusion layer 117 can be increased. In this case,compared to the conventional elevated source/drain structure, theoverlap capacitance C between the floating gate electrode FG andsource/drain diffusion layer 117 can be reduced. This eliminates theproblem of the decrease in operating speed of the transistor Tr.

The gate length (channel length) L2 of the floating gate electrode FG isapproximately 50 nm or less. With this prescribed value, the bird's beakoxidation reaction progresses to the central portion 102 a (channelcentral portion) of the tunnel oxide film 102, thereby realizing apreferable transistor structure. In addition, during gate sidewalloxynitriding, the bird's beak nitriding reaction of the tunnel oxidefilm 102 advances to realize a high-quality film.

Also, the interface nitride layers 115 are formed in the interfacebetween the floating gate electrode FG and tunnel oxide film 102, in theinterface between the floating gate electrode FG and gate sidewall oxidefilm 114, and in the interface between the tunnel oxide film 102 andsilicon substrate 101. Therefore, it is possible to prevent mixing of animpurity from the floating gate electrode FG or silicon substrate 101 tothe tunnel oxide film 102. As a consequence, a low-electric-fieldleakage current of the tunnel oxide film 102 can be suppressed.Therefore, the charge retention characteristics can be improved.

Furthermore, the sidewall portions of the inter-electrode insulatingfilm 108 do not undergo bird's beak oxidation because they are coveredwith the sidewall cover film 118. This make it possible to implement acell transistor Tr having a high cell coupling ratio, and suppressvariations in cell characteristics.

Note that in the second embodiment, after the silicon oxynitride layers112 are formed (FIG. 21), it is also possible to remove the tunnel oxidefilm 102 in the gaps 113 or in low-nitrogen-concentration regions by,e.g., a dilute hydrofluoric acid solution (FIG. 24A), and then form agate sidewall oxide film 114 by thermal oxidation. In this case, asshown in FIG. 24B, oxidation readily progresses near the gaps 113, sothe film thickness of the end portions 102 b of the tunnel oxide film102 can be further increased. Accordingly, the position Cb of the uppersurface of the end portion of the channel region C lowers, so therecession amount Rcb can be further increased. This makes it possible tosuppress the short-channel effect more effectively.

Likewise, after the floating gate electrodes FG are formed (FIG. 20), itis also possible to remove the tunnel oxide film 102 exposed from thefloating gate electrodes FG by, e.g., a dilute hydrofluoric acidsolution (FIG. 25A), and then form silicon oxynitride layers 112. Inthis structure as shown in FIG. 25B, compared to the structure shown inFIG. 13, the position B of the upper surfaces of the source/drain layers117 decreases, and the recession amount Rb increases, but the positionCb of the upper surfaces of the end portions of the cannel region C alsodecreases, and the recession amount Rcb also increases. Therefore, theshort-channel effect can be suppressed as in the structure shown in FIG.13. In addition, it is possible to form the silicon oxynitride layers112 having an oxidation preventing power higher than that of thestructure shown in FIG. 13.

The present invention is not limited to the above embodiments, but canbe variously modified, when practiced, without departing from the spiritand scope of the invention. For example, an SOI (Silicon On Insulator)substrate may also be used.

Additional advantages and modifications will readily occur to thoseskilled in the art. Therefore, the invention in its broader aspects isnot limited to the specific details and representative embodiments shownand described herein. Accordingly, various modifications may be madewithout departing from the spirit or scope of the general inventiveconcept as defined by the appended claims and their equivalents.

1. A semiconductor device comprising: a semiconductor substrate; a gateinsulating film formed on the semiconductor substrate; a gate electrodeformed on the gate insulating film; a source/drain diffusion layerformed in the semiconductor substrate at both sides of the gateelectrode; and a channel region formed in the semiconductor substratebetween a source and a drain of the source/drain diffusion layer andarranged below the gate insulating film, wherein an upper surface of thesource/drain diffusion layer is positioned below a bottom surface of thegate electrode, and an upper surface of the channel region is positionedbelow the upper surface of the source/drain diffusion layer.
 2. Thedevice according to claim 1, wherein a film thickness of the gateinsulating film increases from a center of the channel region toward thesource/drain diffusion layer.
 3. The device according to claim 1,further comprising a nitrogen-containing insulating film formed on thesource/drain diffusion layer.
 4. The device according to claim 3,wherein a nitrogen concentration in a first end portion of thenitrogen-containing insulating film, which is adjacent to the gateelectrode is lower than a nitrogen concentration in a second end portionof the nitrogen-containing insulating film, which is opposite to thefirst end portion of the nitrogen-containing insulating film.
 5. Thedevice according to claim 3, wherein an upper surface of thenitrogen-containing insulating film is positioned below the bottomsurface of the gate electrode.
 6. The device according to claim 1,further comprising a gate sidewall oxide film which is formed on a sidesurface of the gate electrode, and thins from the bottom surface to anupper surface of the gate electrode.
 7. The device according to claim 1,further comprising an interface nitride layer formed in a firstinterface between the gate electrode and gate insulating film, and in asecond interface between the gate insulating film and semiconductorsubstrate.
 8. The device according to claim 1, in which the gateelectrode is a floating gate electrode of a nonvolatile memory celltransistor, and the gate insulating film is a tunnel insulating film,and which further comprises: an inter-electrode insulating film formedon the gate electrode; and a control gate electrode formed on theinter-electrode insulating film.
 9. The device according to claim 8,further comprising a nitrogen-containing insulating film formed on thesource/drain diffusion layer.
 10. The device according to claim 9,wherein a nitrogen concentration in an end portion of thenitrogen-containing insulating film is lower than a nitrogenconcentration in a central portion of the nitrogen-containing insulatingfilm.
 11. A semiconductor device manufacturing method comprising:forming a gate insulating film on a semiconductor substrate; selectivelyforming a gate electrode on the gate insulating film; forming anitrogen-containing insulating film by nitriding an exposed portion ofthe gate insulating film; performing thermal oxidation that an oxideamount at an upper surface of the semiconductor substrate and at abottom surface of the gate electrode reduces from an end portion to acentral portion of a channel region beneath the gate electrode, forminga sidewall layer on a side surface of the gate electrode, and thickeningthe gate insulating film in a lower end portion of the gate electrode;and forming a source/drain diffusion layer in the semiconductorsubstrate.
 12. The method according to claim 11, wherein an uppersurface of the source/drain diffusion layer is positioned below a bottomsurface of the gate electrode, and an upper surface of the channelregion is positioned below the upper surface of the source/draindiffusion layer.
 13. The method according to claim 11, wherein thenitrogen-containing insulating film is formed that a nitrogenconcentration in a first end portion of the nitrogen-containinginsulating film, which is adjacent to the gate electrode is lower than anitrogen concentration in a second end portion of thenitrogen-containing insulating film, which is opposite to the first endportion of the nitrogen-containing insulating film.
 14. The methodaccording to claim 11, further comprising forming a gap between thenitrogen-containing insulating film and an end portion of the gateelectrode.
 15. The method according to claim 11, further comprisingforming an interface nitride layer in a first interface between the gateelectrode and gate insulating film, and in a second interface betweenthe gate insulating film and semiconductor substrate.
 16. The methodaccording to claim 11, wherein the thermal oxidation increases a filmthickness of the gate insulating film from a center of the channelregion toward the source/drain diffusion layer.
 17. The method accordingto claim 11, wherein a film thickness of the sidewall layer decreasesfrom the bottom surface to an upper surface of the gate electrode. 18.The method according to claim 11, further comprising removing the gateinsulating film below an end portion of the gate electrode, after thenitrogen-containing insulating film is formed and before the thermaloxidation is performed.
 19. The method according to claim 11, in whichthe gate electrode is a floating gate electrode of a nonvolatile memorycell transistor, and the gate insulating film is a tunnel insulatingfilm, and which further comprises: forming an inter-electrode insulatingfilm on the gate electrode; and forming a control gate electrode on theinter-electrode insulating film.
 20. The method according to claim 19,wherein an upper surface of the source/drain diffusion layer ispositioned below a bottom surface of the gate electrode, and an uppersurface of the channel region is positioned below the upper surface ofthe source/drain diffusion layer.